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Asynchronous resets take effect immediately, while synchronous resets wait for the next active clock edge. Industry standards heavily favor synchronous resets for general logic because they filter out glitches and ease timing closure.
Reliable digital systems depend entirely on clean clock and reset trees. Poor design choices here cause metastability issues that are incredibly difficult to debug. Clock Principles effective coding with vhdl principles and best practice pdf
Novices try to build entire CPUs inside a single process. Experts know that a process is a jealous container. If you put counter logic and a state machine together, they fight. Asynchronous resets take effect immediately